IBM Z+Arm on 2nm Z+Arm Chip Brings ARM v9.3

IBM is expanding its Z mainframe roadmap with full ARM v9.3 support, aiming to keep the Z series’ long-running “nine nines” availability target while moving a key part of its platform into the ARM ecosystem. The company will showcase the updated Z+Arm approach at Hot Chips 2026, centered around a new, highly specialized processor design built on a 2nm process.

Key takeaways

IBM’s next Z mainframe generation adds full ARM v9.3 support, presented as Z+Arm at Hot Chips 2026.
The new processor uses a 2nm manufacturing process and is built around 11 cores with a base clock of 5.7+ GHz (with headroom for higher clocks).
IBM targets 99.9999999% availability for Z systems, with “Z” also tied to the idea of zero downtime.
The design includes large cache structures: 36 MB L2 cache per core, a combined virtual L3 cache of 432 MB (12 × 36 MB), and an L4 “virtual cache” that can be up to 3.5 GB of system memory.
To support both instruction ecosystems, threads can operate in “Z mode” or “Arm mode,” and IBM says they can compete when multi-thread requests can be handled by either.
IBM is pairing the platform direction with a new enterprise AI accelerator featuring HBM3e, positioned as an inference-focused successor to the Spyre AI card.

IBM Z+Arm: 11 cores, 5.7+ GHz, and “nine nines” availability

Mainframes remain a core business for IBM, especially for workloads where mission-critical transactions run continuously. The company states that IBM mainframes are involved in 70% of financial transactions, and it frames Z as a platform that continues to evolve rather than pause after earlier architecture steps.

The availability goal for the Z line is expressed as 99.9999999% system availability—IBM’s “nine nines” target. IBM also notes that 100% availability doesn’t exist in practice, while pointing out that the “Z” branding is connected to “zero downtime.”

For the processor itself, IBM specifies an 2nm-based chip design with 11 cores clocked at 5.7+ GHz as a baseline, alongside simultaneous multithreading (SMT). The cache hierarchy is a major part of the design: each core includes 36 MB of L2 cache, while a larger virtual L3 cache draws on the combined L2 cache slices for a total of 432 MB (described as 12 × 36 MB). The system also adds an L4 cache mechanism that can designate up to 3.5 GB of system memory as “virtual cache.” IBM says this “virtual cache” approach was previously revealed two years earlier with Telum II, and the new Z is described as an expanded development of that concept.

IBM also includes a DPU and various accelerators in the processor package. Because accelerators take the space of a core, the chip ends up with 11 cores rather than 12.

How IBM blends Z and ARM: mode-switching threads and separated decoders

To enable ARM in the Z environment, IBM says the cores needed several adjustments so they can handle ARM alongside the mainframe side. The result is a thread model that supports two execution modes: “Z mode” and “Arm mode.” IBM also describes internal competition between threads—when multi-thread requests can be fulfilled by either mode, the threads may contend with each other.

IBM’s biggest architectural change toward ARM is described as a separation of the decoder units. While IBM says there are shared resources along the way, the decoder split is presented as the key difference in how the system prepares instructions for the two execution paths. The company positions this as a major step in making the Z platform capable of running ARM workloads without giving up its mainframe-oriented performance and availability focus.

Enterprise AI accelerator with HBM3e targets inference gains

Alongside the Z+Arm direction, IBM is also introducing a new enterprise AI accelerator built with HBM3e. The company frames it as a successor to the Spyre AI card, with performance improvements that it says are substantial due to the age of the previous generation.

IBM also indicates the new accelerator focuses on inference, which it says is a significant part of why the upgrade delivers notable gains. While IBM’s products are aimed at enterprise and data-center deployments rather than consumer hardware, the technical details are positioned as a meaningful update for professional AI workloads.